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1 ds05-11204-1e fujitsu semiconductor data sheet memory cmos 4m 72 bit fast page mode dram module MB85317A-60/-70 cmos 4m 72 bit fast page mode dram module n description the fujitsu mb85317a is a fully decoded, cmos dynamic random access memory (dram) module consisting of eighteen mb8116400a devices. the mb85317a is optimized for those applications requiring high speed, high performance and large memory storage. the operation and electrical characteristics of the mb85317a are the same as the mb8116400a which features fast page mode operation. for ease of memory expansion, the mb85317a is offered in an 168-pad dual in-line memory module package (dimm). n absolute maximum ratings (see note.) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit supply voltage v cc ?.5 to +7.0 v input voltage v in ?.5 to +7.0 v output voltage v out ?.5 to +7.0 v short circuit output current i out 50 ma power dissipation p d 20 w storage temperature t stg ?5 to +125 c this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 MB85317A-60/mb85317a-70 n product line & features n package parameter MB85317A-60 mb85317a-70 ras access time 60 ns max. 70 ns max. random cycle time 110 ns min. 130 ns min. address access time 35 ns max. 40 ns max. cas access time 20 ns max. 22 ns max. fast page mode cycle time 40 ns min. 45 ns min. power dissipation operating mode 9020 mw max. 7920 mw max. standby mode 550 mw max. 550 mw max. conformed to 8-byte dimm jedec standard organization : 4,194,304 words 72 bits (ecc) module size : 1.00 (height) 5.25 (length) 0.157 (thick) memory : mb8116400a (4m 4, 4k ref.), 18 pcs tis input buffers, 2pcs tis input driver for buffered pd, 1pc decou p lin g ca p acitors , 20 p cs 5.0v 10% supply voltage 4,096 refresh cycles / 65.6ms fast page operation ras only refresh / cas -before-ras refresh package and ordering information: 168-pad dimm, order as mb85317a-xxptpbk (ptpbk = gold pad) mds-168p-p04
3 MB85317A-60/mb85317a-70 cas we ras oe fig. 1 ? block diagram dq 68 dq 69 dq 70 dq 71 cas i/o i/o i/o i/o we ras chip 17 oe a 0 a 1 -a 11 dq 32 dq 33 dq 34 dq 35 cas i/o i/o i/o i/o we ras chip 8 oe a 0 a 1 -a 11 oe 0 cas 0 ras 0 we 0 v cc v ss c 0 -c 19 dq 4 dq 5 dq 6 dq 7 i/o i/o i/o i/o chip 1 a 0 a 1 -a 11 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 cas i/o i/o i/o i/o we ras chip 2 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 3 oe a 0 a 1 -a 11 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 cas i/o i/o i/o i/o we ras chip 4 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 5 oe a 0 a 1 -a 11 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 cas i/o i/o i/o i/o we ras chip 6 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 7 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 0 dq 0 dq 1 dq 2 dq 3 oe a 0 a 1 -a 11 oe 2 cas 4 ras 2 we 2 dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 dq 64 dq 65 dq 66 dq 67 dq 36 dq 37 dq 38 dq 39 cas i/o i/o i/o i/o we ras chip 10 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 11 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 12 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 13 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 14 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 15 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 16 oe a 0 a 1 -a 11 cas i/o i/o i/o i/o we ras chip 9 oe a 0 a 1 -a 11 a 0 a 1 -a 11 b 0 sn74abt162244 chip0-19 (drivers, chip18, 19) pde v cc or v ss pd 1 -pd 8 sn74abt2244 (chip20)
4 MB85317A-60/mb85317a-70 n pin assignments (continued) pin no. mb85317a pin no. mb85317a pin no. mb85317a pin no. mb85317a 1v ss 36 a 6 71 dq 30 106 dq 53 2dq 0 37 a 8 72 dq 31 107 v ss 3dq 1 38 a 10 73 v cc 108 nc 4dq 2 39 nc 74 dq 32 109 nc 5dq 3 40 v cc 75 dq 33 110 v cc 6v cc 41 nc 76 dq 34 111 nc 7dq 4 42 nc 77 dq 35 112 nc 8dq 5 43 v ss 78 v ss 113 nc 9dq 6 44 oe 2 79 pd 1 114 nc 10 dq 7 45 ras 2 80 pd 3 115 nc 11 dq 8 46 cas 4 81 pd 5 116 v ss 12 v ss 47 nc 82 pd 7 117 a 1 13 dq 9 48 we 2 83 id 0 118 a 3 14 dq 10 49 v cc 84 v cc 119 a 5 15 dq 11 50 nc 85 v ss 120 a 7 16 dq 12 51 nc 86 dq 36 121 a 9 17 dq 13 52 dq 18 87 dq 37 122 a 11 18 v cc 53 dq 19 88 dq 38 123 nc 19 dq 14 54 v ss 89 dq 39 124 v cc 20 dq 15 55 dq 20 90 v cc 125 nc 21 dq 16 56 dq 21 91 dq 40 126 b 0 22 dq 17 57 dq 22 92 dq 41 127 v ss 23 v ss 58 dq 23 93 dq 42 128 nc 24 nc 59 v cc 94 dq 43 129 nc 25 nc 60 dq 24 95 dq 44 130 nc 26 v cc 61 nc 96 v ss 131 nc 27 we 0 62 nc 97 dq 45 132 pde 28 cas 0 63 nc 98 dq 46 133 v cc 29 nc 64 nc 99 dq 47 134 nc 30 ras 0 65 dq 25 100 dq 48 135 nc 31 oe 0 66 dq 26 101 dq 49 136 dq 54 32 v ss 67 dq 27 102 v cc 137 dq 55 33 a 0 68 v ss 103 dq 50 138 v ss 34 a 2 69 dq 28 104 dq 51 139 dq 56 35 a 4 70 dq 29 105 dq 52 140 dq 57
5 MB85317A-60/mb85317a-70 (continued) pin no. mb85317a pin no. mb85317a pin no. mb85317a pin no. mb85317a 141 dq 58 148 nc 155 dq 66 162 v ss 142 dq 59 149 dq 61 156 dq 67 163 pd 2 143 v cc 150 dq 62 157 v cc 164 pd 4 144 dq 60 151 dq 63 158 dq 68 165 pd 6 145 nc 152 v ss 159 dq 69 166 pd 8 146 nc 153 dq 64 160 dq 70 167 id 1 147 nc 154 dq 65 161 dq 71 168 v cc
6 MB85317A-60/mb85317a-70 n pin descriptions n presence detect (pd)/id definition n capacitance (t a = 25 c, f = 1 mhz) symbol function input/output pin count a 0 to a 11 , b 0 address input input 13 ras 0 and ras 2 row address strobe input 2 cas 0 and cas 4 column address strobe input 2 we 0 and we 2 write enable input 2 oe 0 and oe 2 output enable input 2 dq 0 to dq 71 data-input / data-output input/output 72 pd 1 to pd 8 presence detect output 8 id 0 and id 1 id bit output 2 pde presence detect enable input 1 v cc power supply 16 v ss ground 16 nc no connection 32 symbol MB85317A-60 mb85317a-70 description of pd / id pd 1 h h module density, dram organization and addressing; module density: 32mb, number of bank: 1 bank module con?uration: 4m 72 mounted dram con?uration: 4m 4 dram address (row / column): 12 / 11 pd 2 hh pd 3 ll pd 4 hh pd 5 l l edo detection; fast page mode : pd5 = l pd 6 hl module speed; 60ns : pd6 = h, pd7 = h 70ns : pd6 = l, pd7 = h pd 7 hh pd 8 l l ecc / parity detection; ecc : pd8 = l id 0 l l module type; x72 ecc : id0 = l id 1 l l refresh mode; normal refresh : id1 = l parameter symbol min. max. unit input capacitance, (address) c in1 ?0pf input capacitance, (ras )c in2 ?0pf input capacitance, (cas , we , oe )c in3 ?0pf i/o capacitance, (dq) c dq ?0pf
7 MB85317A-60/mb85317a-70 n recommended operating condition (referenced to v ss ) note: *undershoots of up to -1.5volts with a pulse width not exceeding 10ns are acceptable. n dc characteristics (recommended operating conditions unless otherwise noted.) notes: *1 referenced to v ss . *2 i cc depends on the output load conditions and cycle rate. the speci? values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih , v il > -0.3v. i cc1 , i cc3 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . i cc4 is speci?d at one time of address change during one page cycle. parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v ground v ss ?v input high voltage, all inputs v ih 2.4 6.0 v input low voltage, all inputs * v il ?.3 0.8 v ambient temperature t a 070 c parameter test condition symbol min. max. unit output high voltage * 1 i oh = -5ma v oh 2.4 v output low voltage * 1 i ol = 4.2ma v ol 0.4 v input leakage current ras 0v v in 5.5v, 4.5v v cc 5.5v, v ss = 0v, all other pins not under test = 0v i i(l) ?0 50 m a others ?0 10 output leakage current 0v v out 5.5v, 4.5v v cc 5.5v, data out disabled i o(l) ?0 10 m a operating current * 2 (average power supply current) MB85317A-60 ras & cas cycling, t rc = min. i cc1 1640 ma mb85317a-70 1440 standby current * 2 (power supply current) ttl level ras = cas = pde = v ih i cc2 100 ma cmos level ras = cas = pde 3 v cc ?.2v 80 refresh current #1 * 2 (average power supply current) MB85317A-60 cas = v ih , ras = cycling, t rc = min. i cc3 1640 ma mb85317a-70 1440 fast page mode current * 2 MB85317A-60 ras = v il , cas = cycling, t pc = min. i cc4 1640 ma mb85317a-70 1440 refresh current #2 * 2 (average power supply current) MB85317A-60 ras = cycling, cas -before-ras , t rc = min. i cc5 1640 ma mb85317a-70 1440
8 MB85317A-60/mb85317a-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 no. parameter symbol MB85317A-60 mb85317a-70 unit notes min. max. min. max. 1 time between refresh t ref 65.6 65.6 ms 2 random read/write cycle time t rc 110 130 ns 3 read-modify-write cycletime t rwc 150 174 ns 4 access time from ras t rac 60 70 ns 4,7 5 access time from cas t cac 20 22 ns 5,7 6 column address access time t aa 35 40 ns 6,7 7 output hold time t oh 5?ns 8 output buffer turn on delaytime t on 2?ns 9 output buffer turn off delay time t off 20 22 ns 8 10 transition time t t 216216ns 11 ras precharge time t rp 40 50 ns 12 ras pulse width t ras 60 100000 70 100000 ns 13 ras hold time t rsh 20 22 ns 14 cas to ras precharge time t crp 5?ns 15 ras to cas delay time t rcd 18 40 18 48 ns 9,10 16 cas pulse width t cas 15 17 ns 17 cas hold time t csh 58 68 ns 18 cas precharge time (c-b-r refresh) t cpn 10 10 nss 17 19 row address setup time t asr 5?ns 20 row address hold time t rah 8?ns 21 column address setup time t asc 0?ns 22 column address hold time t cah 15 15 ns 23 column address hold time from ras t ar 33 33 ns 24 ras to column address delay time t rad 13 25 13 30 ns 11 25 column address to ras lead time t ral 35 40 ns 26 column address to cas lead time t cal 30 35 ns 27 read command setup time t rcs 0?ns 28 read command hold time referenced to ras t rrh ? 2 ns 12 29 read command hold time referenced to cas t rch 0?ns12
9 MB85317A-60/mb85317a-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 no. parameter symbol MB85317A-60 mb85317a-70 unit notes min. max. min. max. 30 write command setup time t wcs 0?ns 13,18 31 write command hold time t wch 15 15 ns 32 write command hold time from ras t wcr 33 33 ns 33 we pulse width t wp 15 15 ns 34 write command to ras lead time t rwl 20 22 ns 35 write command to cas lead time t cwl 15 17 ns 36 din setup time t ds ? 2 ns 37 din hold time t dh 20 20 ns 38 data hold time from ras t dhr 35 35 ns 39 ras to we delay time t rwd 78 90 ns 18 40 cas to we delay time t cwd 35 39 ns 18 41 column address to we delay time t awd 50 57 ns 18 42 ras precharge time to cas active time (refresh cycles) t rpc 3?ns 43 cas setup time (c-b-r refresh) t csr 5?ns 44 cas hold time (c-b-r refresh) t chr 8 10 ns 45 we setup time from ras t wsr 5?ns 46 we hold time from ras t whr 8?ns 47 access time from oe t oea 20 22 ns 7 48 output buffer turn off delay from oe t oez 20 22 ns 8 49 oe to ras lead time for valid data t oel 10 12 ns 50 we hold time referenced to we t oeh 5?ns14 51 oe to data in delay time t oed 20 22 ns 52 cas to data in delay time t cdd 20 22 ns 53 din to cas delay time t dzc ? 2 ns 15 54 din to oe delay time t dzo ? 2 ns 15 55 fast page mode ras pulse width t rasp 100000 100000 ns 56 fast page mode read/write cycle time t pc 40 45 ns
10 MB85317A-60/mb85317a-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 no. parameter symbol MB85317A-60 mb85317a-70 unit notes min. max. min. max. 57 fast page mode read-modify- write cycle time t prwc 80 89 ns 58 access time from cas precharge t cpa 40 45 ns 7, 16 59 fast page mode cas precharge time t cp 10 10 ns 60 fast page mode ras hold time from cas precharge t rhcp 40 45 ns 61 fast page mode cas precharge to we delay time t cpwd 55 62 ns 18
11 MB85317A-60/mb85317a-70 notes: 1. an initial pause (ras =cas =v ih ) of 200 m s is required after power-up followed by any eight ras -only cycles before proper device operation is achieved. if an internal refresh counter is used, a minimum of eight cas -before-ras initialization cycles are required instead of eight ras cycles. 2. ac characteristics assume t t = 5ns. 3. v ih (min.) and v il (max.) are reference levels for measureing the timing of input signals. transition times are measured between v ih (min.) and v il (max.). 4. assumes that t rcd t rcd (max.), t rad t rad (max.). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. 5. if t rcd 3 t rcd (max.), t rad 3 t rad (max.), and t asc 3 t aa ?t cac ?t t , access time is t cac . 6. if t rad 3 t rad (max.) and t asc t aa ?t cac ?t t , access time is t aa . 7. measured with a load equivalent to two ttl loads and 100 pf. 8. t off is speci?d that output buffer change to high impedance state. 9. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max.) limit, access time is controlled exclusively by t cac or t aa . 10. t rcd (min.) = t rah (min.)+ 2t t + t asc (min.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max.) limit, access time is controlled exclusively by t cac or t aa . 12. either t rrh or t rch must be satis?d for a read cycle. 13. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min.) the data output pin will remain high-z state through entire cycle. 14. assumes that t wcs < t wcs (min.). 15. either t dzc or t dzo must be satis?d. 16. t cpa is access time from the selection of a new column address (caused by changing cas from ? to ??. therefore, if t cp become long, t cpa also become longer than t cpa (max.). 17. assumes that cas -before-ras refresh. 18. t wcs , t cwd , t rwd , t awd , and t cpwd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs 3 t wcs (min.), the cycle is an early write cycle and dout pin will maintain high impedance state thoughout the entire cycle. if t cwd 3 t cwd (min.), t rwd 3 t rwd (min.), t awd 3 t awd (min.), and t cpwd 3 t cpwd (min.), the cycle is a read-modify-write cycle and data from the selected cell will appear at the dout pin. if neither of the above conditions is satis?d, the cycle is a delayed write cycle and invalid data will appear the dout pin, and write operation can be executed by satisfying t rwl , t cwl , t ral and t cal speci?ations. *source: see mb8116400a data sheet for details on the electricals.
12 MB85317A-60/mb85317a-70 n package dimensions (suf?: ptpbk) +0.10 C0.08 +.004 C.003 4.00(.157)max details of "a" part 1.000.05(.039.002) 6.350.13(.250.005) 2.000.10(.079.004) 3.00(.118) 3.25(.128) (.250.005) 6.350.13 1.000.05(.039.002) 2.000.10(.079.004) 4.00(.157)min details of "b" part 0.25(.010)max 2.54(.100)typ l c 3.00(.118) 3.25(.128) details of "c" part (.039.002) 1.000.05 "c" "b" "a" notches full r (.700.005) 17.780.13 1.27 .050 pin no.1 index 127.350.10(5.014.004) 115.570.13(4.550.005) 54.610.05(2.150.002) (.050.001) 1.270.03 l c (.450.005) 11.430.05 63.680.13(2.507.005) 43.180.13(1.700.005) (1.450.002) 36.830.05 (.125.005) 3.170.13 (1.000.005) 25.400.13 (.118.005) 3.000.13 (?.118.002) ?3.000.05 (.157.005) 4.000.13 3.00(.118)min and 4.00 notch component area 133.350.13(5.250.005) 131.350.13(5.171.005) l c 66.680.13(2.625.005) 65.680.13(2.586.005) 168 85 1 84 1994 fujitsu limited m168004sc-1-1 c 168 pin, plastic dimm (mds-168p-p04) dimensions in mm(inches).
24 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9703 fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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